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quad, 12-/14-/16-bit nano dacs with 5 ppm/c on-chip reference data sheet AD5624R / ad5644r / ad5664r rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2006C2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power, smallest pin-compatible, quad nano dacs ad5664r: 16 bits ad5644r: 14 bits AD5624R: 12 bits user-selectable external or internal reference external reference default on-chip 1.25 v/2.5 v, 5 ppm/c reference 10-lead msop; 10-lead, 3 mm 3 mm lfcsp_wd; and 12-ball, 1.665 mm 2.245 mm wlcsp 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale per channel power-down serial interface, up to 50 mhz applications process controls data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram figure 1. table 1. related devices part no. description ad5624/ ad5664 2.7 v to 5.5 v quad, 12-/16-bit dacs, external reference ad5666 2.7 v to 5.5 v quad, 16-bit dac, internal reference, ldac , clr pins general description the AD5624R/ad5644r/ad5664r, members of the nano dac? family, are low power, quad, 12-/14-/16-bit buffered voltage-out dacs. all devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the AD5624R/ad5644r/ad5664r have an on-chip reference. the ad56x4r-3 has a 1.25 v, 5 ppm/c reference, giving a full- scale output range of 2.5 v; the ad56x4r-5 has a 2.5 v, 5 ppm/c reference giving a full-scale output range of 5 v. the on-chip reference is off at power-up, allowing the use of an external reference; all devices can be operated from a single 2.7 v to 5.5 v supply. the internal reference is enabled via a software write. the part incorporates a power-on reset circuit that ensures the dac output powers up to 0 v and remains there until a valid write takes place. the part contains a per-channel power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. the AD5624R/ad5644r/ad5664r use a versatile 3-wire serial interface that operates at clock rates up to 50 mhz, and is com- patible with standard spi, qspi?, microwire?, and dsp interface standards. the on-chip precision output amplifier enables rail-to-rail output swing. product highlights 1. quad 12-/14-/16-bit dacs. 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 10-lead msop; 10-lead, 3 mm 3 mm lfcsp_wd; and 12-ball, 1.665 mm 2.245 mm wlcsp. 4. low power, typically consumes 1.32 mw at 3 v and 2.25 mw at 5 v. 0 5856-001 buffer buffer AD5624R/ad5644r/ad5664r 1.25v/2.5v ref v dd v refin / v refout gnd power- down logic power-on logic sclk s ync din string dac a string dac b string dac c string dac d dac register dac register dac register dac register input register input register input register input register interface logic buffer buffer v out a v out b v out c v out d
AD5624R/ad5644r/ad5664r data sheet rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 AD5624R - 5/ad56 44r - 5/ad5664r - 5 ...................................... 3 AD5624R - 3/ad5644r - 3/ad5664r - 3 ...................................... 4 ac characteristics ........................................................................ 6 timing characteristics ................................................................ 7 timing diagram ........................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 18 theory of operation ...................................................................... 20 digital - to - analog section ......................................................... 20 resistor string ............................................................................. 20 output ampli fier ........................................................................ 20 internal reference ...................................................................... 20 external reference ..................................................................... 20 serial interface ............................................................................ 20 input shift register .................................................................... 21 sync interrupt ........................................................................... 21 power - on reset .......................................................................... 22 software reset ............................................................................. 22 power - down mod es .................................................................. 22 ldac function ........................................................................... 23 internal reference setup ........................................................... 23 microprocessor interfacing ....................................................... 24 ap plications information .............................................................. 25 using a reference as a power supply for the AD5624R/ad5644r/ad5664r ............................................... 25 bipolar operation using the AD5624R/ad5644r/ad5664r ....................................................................................................... 25 using AD5624R/ad5644r/ad5664r with a galvanically isolated interface ........................................................................ 25 power supply bypassing and grounding ................................ 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 28 revision history 4 /13 rev. b to rev. c added 12 - ball wlcsp ...................................................... universal changes to features and product highlights sections ................ 1 change to reference tc parameter, table 2 ................................. 3 added thermal impedance, wlcsp package (4 - layer board) , ja parameter, table 6 ....................................................................... 8 added figure 4 ; renumbered sequentially .................................. 9 changes to figure 3 caption and table 7 ...................................... 9 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 4/08 rev. a to rev. b changes to figure 50 ...................................................................... 20 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 11/06 rev. 0 to rev . a changes to reference output paramet er in table 2 ..................... 3 changes to reference output parameter in table 3 ..................... 5 added note to figure 3 .................................................................... 9 4/06 revision 0: initial version
data sheet AD5624R/ad5644r/ad5664r rev. c | page 3 of 28 specifications AD5624R - 5/ad5644r - 5/ad5664r - 5 v dd = 4.5 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 2 . b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5664r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5644r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design AD5624R resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero - code error 2 10 mv all zeroes loaded to dac register offset error 1 10 mv full - scale error ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 % of fsr zero - code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale ; v dd = 5 v 10% dc crosstalk external reference 10 v due to full - scale output change, r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) internal reference 25 v due to full - scale output change, r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short - circuit current 30 ma v dd = 5 v power - up time 4 s coming out of power - down mode; v dd = 5 v reference inputs reference current 170 200 a v ref = v dd = 5.5 v reference input range 0.75 v dd v reference input impedance 26 k reference output output voltage 2.495 2.505 v at ambient reference tc 3 5 10 ppm/c msop package models 10 ppm/c lfcsp package models 15 ppm/c wlcsp package models output impedance 7.5 k
AD5624R/ad5644r/ad5664r data sheet rev. c | page 4 of 28 b grade 1 parameter min typ max unit conditions/comments logic inputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 5 v v inh , input high voltage 2 v v dd = 5 v pin capacitance 3 pf power requirements v dd 4.5 5.5 v i dd v ih = v dd , v il = gnd, v dd = 4.5 v to 5.5 v normal mode 4 0.45 0.9 ma internal reference off 0.95 1.2 ma internal reference on all power - down modes 5 0.48 1 a 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad5664r (code 512 to code 65,024); ad5644r (code 128 to code 16,256); ad5624 r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inacti ve. all dacs active. dac outputs unloaded. 5 all dacs powered down. AD5624R - 3/ad5644r - 3/ad5664r - 3 v dd = 2.7 v to 3.6 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 3 . b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5664r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5644r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design AD5624R resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero - code error 2 10 mv all zeroes loaded to dac register offset error 1 10 mv full - scale error ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 % of fsr zero - code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale; v dd = 3 v 10% dc cro sstalk external reference 10 v due to full - scale output change, r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) internal reference 25 v due to full - scale output change, r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel)
data sheet AD5624R/ad5644r/ad5664r rev. c | page 5 of 28 b grade 1 parameter min typ max unit conditions/comments output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short - circuit current 30 ma v dd = 3 v power - up time 4 s coming out of power - down mode; v dd = 3 v reference inputs reference current 170 200 a v ref = v dd = 3.6 v reference input range 0 v dd v reference input impedance 26 k reference output output voltage 1.247 1.253 v at ambient reference tc 3 5 15 ppm/c msop package models 10 ppm/c lfcsp package models output impedance 7.5 k logic inputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 3 v v inh , input high voltage 2 v v dd = 3 v pin capacitance 3 pf power requirements v dd 2.7 3.6 v i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 3.6 v normal mode 4 0.44 0.85 ma internal reference off 0.95 1.15 ma internal reference on all power - down modes 5 0.2 1 a 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad5664r (code 512 to code 65,024); ad5644r (code 128 to code 16,256); ad5624 r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down.
AD5624R/ad5644r/ad5664r data sheet rev. c | page 6 of 28 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. 1 table 4 . parameter 2 min typ max unit conditions/comments 3 output voltage settling time AD5624R 3 4.5 s ? to ? scale settling to 0.5 lsb ad5644r 3.5 5 s ? to ? scale settling to 0.5 lsb ad5664r 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital - to - analog glitch impulse 10 nv - s 1 lsb change around major carry digital feedthrough 0.1 nv - s reference feedthrough ?90 db v ref = 2 v 0.1 v p - p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv - s analog crosstalk 1 nv - s external reference 4 nv - s internal reference dac -to - dac crosstalk 1 nv - s external reference 4 nv - s internal reference multiplying bandwidth 340 khz v ref = 2 v 0.1 v p -p total harmonic distortion ?80 db v ref = 2 v 0.1 v p - p, frequency = 10 khz output noise spectral density 120 nv/ hz dac code = midscale, 1 khz 100 nv/ hz dac code = midscale, 10 khz output noise 15 v p -p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typical at 25c.
data sheet AD5624R/ad5644r/ad5664r rev. c | page 7 of 28 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2 (see figure 2 ). v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. 1 table 5 . limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 2 20 ns min sclk cycle time t 2 9 ns min sclk high time t 3 9 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore 1 guaranteed by design and characterization, not production tested. 2 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. timing diagram figure 2 . serial write operation db0 db23 t 10 sclk sync din t 1 t 9 t 7 t 2 t 3 t 6 t 5 t 4 t 8 05856-002
AD5624R/ad5644r/ad5664r data sheet rev. c | page 8 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja thermal impedance lfcsp_wd package (4 - layer board) ja 61c/w msop package (4 - layer board) ja 142c/w jc 43.7c/w wlcsp package (4 - layer board) ja 75 c/w reflow soldering peak temperature pb - free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet AD5624R/ad5644r/ad5664r rev. c | page 9 of 28 pin configuration s and function descrip tions figure 3. 10 - lead lfcsp and 10 - lead msop pin configuration figure 4 . 12 - ball wlcsp pin configuration table 7 . pin function descriptions pin no. lfcsp msop wlcsp mnemonic description 1 1 a3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 2 b3 v out b analog output voltage from dac b. the output amplifier has rail - to - rail operation. 3 3 a2, b2, c2 gnd ground reference point for all circuitry on the part. 4 4 c3 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. 5 5 d3 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. 6 6 d2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the next 24 clocks. if sync is taken high before the 24 th falling edge, the rising edge of sync acts as an interrupt and th e write sequence is ignored by the device. 7 7 d1 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 50 mhz. 8 8 c1 din serial data input. this device has a 24 - bit shift register. data is clocked into the register on the falling edge of the serial clock input. 9 9 b1 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f ca pacitor in parallel with a 0.1 f capacitor to gnd. 10 10 a1 v refin /v refout the AD5624R/ad5644r/ad5664r have a common pin for reference input and reference output. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. n/a n/a epad exposed pad. the exposed pad must be tied to gnd on the lfcsp package. 1 v out a 10 v refin /v refout 2 v out b 9 v dd 3 gnd 8 din 4 v out c 7 sclk 5 v out d 6 sync AD5624R/ ad5644r/ ad5664r top view (not to scale) 05856-003 exposed p ad tied t o gnd on lfcs p p ackage t op view (bal l side down) not to scale gnd v out a v dd gnd v out b din gnd v out c sclk sync v out d 1 a b c d 2 3 bal l a1 indic a t or 05856-104 v refin / v refout
AD5624R/ad5644r/ad5664r data sheet rev. c | page 10 of 28 typical performance characteristics figure 5 . ad5664r inl , external reference figure 6 . ad5644r inl , external reference figure 7 . AD5624R inl , external reference figure 8 . ad5664r dnl , external reference figure 9 . ad5644r dnl , external reference figure 10 . AD5624R dnl , external reference code in l error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 05856-004 v dd = v ref = 5v t a = 25c code in l error (lsb) 4 ?4 0 2500 5000 7500 10000 12500 15000 05856-005 ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c code in l error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05856-006 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c code dn l error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k 05856-007 v dd = v ref = 5v t a = 25c dn l error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 05856-008 v dd = v ref = 5v t a = 25c code 0 2500 5000 7500 10000 12500 15000 dn l error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 05856-009 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c
data sheet AD5624R/ad5644r/ad5664r rev. c | page 11 of 28 figure 11 . ad5664r - 5 inl , internal reference figure 12 . ad5644r - 5 inl , internal reference figure 13 . AD5624R - 5 inl , internal reference figure 14 . ad5664r - 5 dnl , internal reference figure 15 . ad5644r - 5 dnl , internal reference figure 16 . AD5624R - 5 dnl , internal reference code in l error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 05856-010 c o d e in l error (lsb) 4 3 ? 4 ? 3 ? 2 2 ? 1 1 0 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 05856-011 c o d e inl error (lsb) 1 . 0 0 . 8 0 ? 1 . 0 ? 0 . 8 ? 0 . 6 0 . 6 ? 0 . 4 ? 0 . 2 0 . 4 0 . 2 0 10 0 0 5 0 0 20 0 0 15 0 0 35 0 0 30 0 0 25 0 0 40 0 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 05856-012 c o d e dn l error (lsb) 1 . 0 0 . 8 0 ? 1 . 0 ? 0 . 6 ? 0 . 8 ? 0 . 4 0 . 6 ? 0 . 2 0 . 4 0 . 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 05856-013 code dn l error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 05856-014 code dn l error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 05856-015
AD5624R/ad5644r/ad5664r data sheet rev. c | page 12 of 28 figure 17 . ad5664r - 3 inl , internal reference figure 18 . ad5644r - 3 inl , internal reference figure 19 . AD5624R - 3 inl , internal reference figure 20 . ad5664r - 3 dnl , internal reference figure 21 . ad5644r - 3 dnl , internal reference figure 22 . AD5624R - 3 dnl , internal reference code in l error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 05856-016 v dd = 3v v refout = 1.25v t a = 25c code in l error (lsb) 4 ?4 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 05856-017 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25c code in l error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25c 05856-018 code dn l error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 05856-019 code dn l error (lsb) 0.5 ?0.5 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25c 05856-020 code dn l error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25c 05856-021
data sheet AD5624R/ad5644r/ad5664r rev. c | page 13 of 28 figure 23. inl error and dnl error vs. temperature figure 24. inl error and dnl error vs. v ref figure 25. inl error and dnl error vs. supply figure 26. gain error and full-scale error vs. temperature figure 27. zero-scale error and offset error vs. temperature figure 28. gain error and full-scale error vs. supply temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 200 100 80 60 05856-022 min dnl max dnl max inl min inl v dd = v ref = 5v v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 min dnl max dnl max inl min inl v dd = 5v t a = 25c 05856-023 v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 min dnl max dnl max inl min inl t a = 25c 05856-024 temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 20 0100 80 60 v dd = 5v gain error full-scale error 05856-025 temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 080 60 100 offset error zero-scale error 05856-026 v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 05856-027
AD5624R/ad5644r/ad5664r data sheet rev. c | page 14 of 28 figure 29 . zero - scale error and offset error vs. supply figure 30 . i dd histogram with external reference, 5.5 v figure 31 . i dd histogram with internal reference, v refout = 2.5 v figure 32 . i dd histogram with external reference, 3.6 v figure 33 . i dd histogram with internal reference, v refout = 1.25 v figure 34 . headroom at rails vs. source and sink v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 05856-028 i dd (ma) frequenc y 0 1 2 3 4 5 6 0.41 0.42 0.43 0.44 0.45 05856-029 v dd = 5.5v t a = 25 c i dd (ma) frequenc y 0 1 2 3 4 5 6 0.92 0.94 0.96 0.98 05856-030 v dd = 5.5v t a = 25 c i dd (ma) frequenc y 0 1 2 3 5 4 6 8 7 0.39 0.40 0.41 0.42 0.43 05856-060 v dd = 3.6v t a = 25 c i dd (ma) frequenc y 0 1 2 3 5 4 6 8 7 0.90 0.92 0.94 0.96 05856-061 v dd = 3.6v t a = 25 c current (ma) error vo lt age (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 10 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 05856-031
data sheet AD5624R/ad5644r/ad5664r rev. c | page 15 of 28 figure 35 . ad56x4r - 5 source and sink capability figure 36 . ad56x4r - 3 source and sink capability figure 37 . supply current vs. temperature figure 38 . full - scale settling time, 5 v figure 39 . power - on reset to 0 v figure 40 . exiting power - down to midscale current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25c zero scale ful l scale midscale 1/4 scale 3/4 scale 05856-046 current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale ful l scale midscale 1/4 scale 3/4 scale 05856-047 temperature (c) i dd (ma) 0.50 0.05 0.10 0.15 0.20 0.35 0.40 0.25 0.30 0.45 0 ?40 ?20 0 20 40 60 80 100 05856-063 t a = 25c v dd = v refin = 5v v dd = v refin = 3v time base = 4 s/div v dd = v ref = 5v t a = 25 c full-scale code change 0x0000 t o 0xffff output loaded with 2k ? and 200pf t o gnd v out = 909mv/div 1 05856-048 ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25 c v out v dd 1 2 max(c2) 420.0mv 05856-049 05856-050 v dd = 5v sync sclk v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2
AD5624R/ad5644r/ad5664r data sheet rev. c | page 16 of 28 figure 41 . digital - to- analog glitch impulse (negative) figure 42 . analog crosstalk, external reference figure 43 . analog crosstalk, 2.5 v internal reference figure 44 . 0.1 hz to 10 hz output noise plot, external reference figure 45 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 46 . 0.1 hz to 10 hz output noise plot, 1.25 v internal reference sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 05856-058 v dd = v ref = 5v t a = 25 c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 t o 0x7fff) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 05856-059 v dd = v ref = 5v t a = 25 c 5ns/sample number analog cross t alk = 0.424nv sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 05856-062 v dd = 5v v refout = 2.5v t a = 25 c 5ns/sample number analog cross t alk = 4.462nv 1 y axis = 2 v/div x axis = 4s/div v dd = v ref = 5v t a = 25 c dac loaded with midscale 05856-051 5s/div 10 v/div 1 v dd = 5v v refout = 2.5v t a = 25 c dac loaded with midscale 05856-052 4s/div 5 v/div 1 v dd = 3v v refout = 1.25v t a = 25 c dac loaded with midscale 05856-053
data sheet AD5624R/ad5644r/ad5664r rev. c | page 17 of 28 figure 47 . noise spectral density, internal reference figure 48 . total harmonic distortion figure 49 . settling time vs. capacitive load figure 50 . multiplying bandwidth frequenc y (hz) output noise (nv/hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 100k 1m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 05856-054 frequenc y (hz) amplitude (db) ?20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with ful l scale v ref = 2v 0.3v p-p 05856-055 ca p aci t ance (nf) time (s) 16 14 12 10 8 6 4 0 1 2 3 4 5 6 7 9 8 10 v ref = v dd t a = 25c v dd = 5v v dd = 3v 05856-056 frequency (hz) amplitude (db) 5 ?40 10k 100k 1m 10m ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 v dd = 5v t a = 25c 05856-057
AD5624R/ad5644r/ad5664r data sheet rev. c | page 18 of 28 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the m aximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 5 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 8 . zero - code error zero - scale error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is alw ays positive in the ad5664r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of zero - code error vs. temperature can be seen in figure 27. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range. a plot of full - scale error vs. temperature can be seen in figure 26. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. zero - code error drift this is a measurement of the change in zero - code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference bet ween v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5664r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in db. v ref is held at 2 v, and v dd is varied by 10%. output vo ltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change and is measured from the 24 th falling edge of sclk. digital -to - analog glitch impulse digital - to - analog glitc h impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s, and is measured when the digital input code is changed by 1 lsb at the major carry t ransition (0x7fff to 0x8000) (see figure 41). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of t he dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s, and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough referen ce feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generated random noise. ran dom noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density can be seen in figure 47. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on o ne dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - s.
data sheet AD5624R/ad5644r/ad5664r rev. c | page 19 of 28 analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code wa s not changed. the area of the glitch is expressed in nv - s. dac -to - dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitor - ing the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv - s. multiplying bandwi dth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db.
AD5624R/ad5644r/ad5664r data sheet rev. c | page 20 of 28 theory of operation d igital - to - a nalog section the AD5624R/ad5644r/ad5664r dacs are fabricated on a cmos process. the archi tecture consists of a string dac followed by an output buffer amplifier. figure 51 shows a block diagram of the dac architecture. figure 51 . dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d v v 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for AD5624R (12 bit). 0 to 16,383 for ad5644r (14 bit). 0 to 65,535 for ad5664r (16 bit). n is the dac resolution. resistor string the resistor string is shown in figure 52 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at whic h node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amp lifier the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be see n in figure 34 and figure 35 . the slew rate is 1.8 v/s with a ? to ? full - scale settling time of 7 s. figure 52 . resistor string internal reference the AD5624R/ad5644r/ad5664r on - chip reference is off at power - up and is enabled via a write to a control register. see the internal reference setup section for details. the ad56x4r - 3 has a 1.25 v, 5 ppm/c reference giving a full - scale output of 2.5 v. the ad56x4r - 5 has a 2.5 v, 5 ppm/c reference giving a full - scale output of 5 v. the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads . when using the internal reference, it is recommended that a 100 nf capacitor is placed between reference output and gnd for reference stability. external reference the v refin pin on the ad56x4r - 3 and ad56x4r - 5 allows the use of an external reference if t he application requires it. the default condition of the on - chip reference is off at power - up. all devices (ad56x4r - 3 and the ad56x4r - 5) can be operated from a single 2.7 v to 5.5 v supply. serial interface the AD5624R/ad5644r/ad5664r have a 3 - wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as with most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24 - bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the AD5624R/ad5644r/ad5664r compat - ible with high speed dsps. on the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a chan ge in the mode of operation. dac register v dd gnd v out output amplifier (gain = +2) 05856-032 v refin resistor string ref r r r r r to output amplifier 05856-033
data sheet AD5624R/ad5644r/ad5664r rev. c | page 21 of 28 at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation. as mentione d previously, it must, however, be brought high again just before the next write sequence. input shift register the input shift register is 24 bits wide (see figure 53 ). the first two bits are dont care bits. the next three are the command bits, c2 to c0 (see table 8 ), followed by the 3 - bit dac address, a2 to a0 (see table 9 ), and then the 16 - , 14 - , 12 - bit data - word. the data - word comprises the 16 - , 14 - , 12 - bit input code followed by 0, 2, or 4 dont care bits, for the ad5664r, ad5644r, and AD5624R, respectively (see figure 53, figure 54, and figure 55 ). these data bits are transferred to the dac register on the 24 th falling edge of sclk. table 8 . command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n, update all (software ldac) 0 1 1 write to and update dac channel n 1 0 0 power down dac (power - up) 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on/off ) table 9 . address command a2 a1 a0 address ( n ) 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 1 1 all dacs sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24 th falling edge. however, if sync is brought high before the 24 th falling edge, then this acts as an interrupt to the write sequence. the input shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 56). figure 53 . ad5664r input shift register contents figure 54 . ad5644r input shift register contents figure 55 . AD5624R input shift register contents figure 56 . sync interrupt facility x x c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-034 x x c2 c1 c0 a2 a1 a0 x x d11 d10 d13 d12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-035 x x c2 c1 c0 a2 a1 a0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-036 din db23 db23 db0 db0 valid write sequence, output updates on the 24 th falling edge sync sclk invalid write sequence: sync high before 24 th falling edge 05856-037
AD5624R/ad5644r/ad5664r data sheet rev. c | page 22 of 28 power - on reset the AD5624R/ad5644r/ad5664r family contains a power - on reset circuit that controls the output voltage during power - up. the output of the AD5624R/ad5644r/ad5664r dacs power s up to 0 v and t he output remains there until a valid write sequence is made to the dacs. this is useful in applications where it is important to know the state of the output of the dacs while they are in the process of powering up. software reset the AD5624R/ad5644r/ad56 64r contain a software reset function. command 101 is reserved for the software reset function (see table 8 ). the software reset command contains two reset modes that are software programmable by setting bit db0 in the control register. table 10 shows how the state of the bit corresponds to the s oftware reset modes of operation of the devices. table 12 shows the contents of the input shift register during the software reset mode of operatio n. table 10. software reset modes for the AD5624R/ad5644r/ad5664r db0 registers reset to 0 0 dac register input shift register 1 (power - on reset) dac register input shift register ldac register power - down register internal reference setup register power - down modes the AD5624R/ad5644r/ ad5664r contain four separate modes of operation. command 100 is reserved for the power - down function (see table 8 ). these modes are software programmable by setting two bits (db5 and db4) in the control register. table 11 shows how the state of the bits corresponds to the mode of operation of the device. all dacs (dac d to dac a) can be powered down to the selected mode by setting the correspond - ing four bits (db3, db2, db1, and db0) to 1. by executing the same command 1 00, any combination of dacs can be powered up by setting the bits (db5 and db4) to normal operation mode. to select which combination of dac channels to power - up, set the corresponding four bits (db3, db2, db1, and db0) to 1. see table 13 for contents of the input shift register during power - down/power - up operation. table 11 . modes of ope ration for the AD5624R/ad5644r/ ad5664r db5 db4 operating mode 0 0 normal operation 0 1 power - down mode: 1 k to gnd 1 0 power - down mode: 100 k to gnd 1 1 power - down mode: t hree - state when bit db5 and bit db4 are set to 0, the part works normally with its normal power consumption of 450 a at 5 v. however, for the three power - down modes, the supply current falls to 480 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this all ows the output impedance of the part to be known while the part is in power - down mode. the outputs can either be connected internally to gnd through a 1 k resistor, or left open - circuited (three - state) as shown in fig ure 57. figure 57 . output stage during power - down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shu tdown when power - down mode is activated. however, the contents of the dac register are unaffected when in power - down. the time to exit power - down is typically 4 s for v dd = 5 v and for v dd = 3 v (see figure 40 ). table 12 . 24- bit input shift register contents for software reset command db23 to db22 (msb) db21 db20 db19 db18 db17 db16 db15 to db1 db0 (lsb) x 1 0 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0) dont care determines software reset mode table 13. 24- bit input shift register contents of power - down/power - up operation for the AD5624R/ad5644r/ad5664r db23 to db22 (msb) db21 db20 db19 db18 db17 db16 db15 to db6 db5 db4 db3 db2 db1 db0 (lsb) x 1 0 0 x x x x pd1 pd0 dac d dac c dac b dac a dont care command bits (c2 to c0) address bits (a2 to a0) dont care dont care power - down mode power - down/power - up channel selection, set bit to 1 to select channel resistor network v out resistor string dac power-down circuitry amplifier 05856-038
data sheet AD5624R/ad5644r/ad5664r rev. c | page 23 of 28 ldac function the AD5624R/ad5644r/ad5664r dacs have double - buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is trans - ferred to the relevant input register on comp letion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. the double - buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user can write to three of the input regi sters individually and then write to the remaining input register, updating all dac registers simulta - neously . command 010 is reserved for this software ldac. access to the dac registers is controlled by the ldac function . the ldac register contains two modes of operation for each dac channel. the dac channels are selected by setting the bits of the 4 - bit ldac register (db3, db2, db1, and db0). command 110 is reserved for setting up the ldac register. when the ldac bit re gister is set low, the corresponding dac registers are latched and the input registers can change state without affecting the contents of the dac registers. when the ldac bit register is set high, however, the dac registers become transparent and the conte nts of the input registers are transferred to them on the falling edge of the 24 th sclk pulse . this is equivalent to having an ldac hardware pin tied perma - nently low for the selected dac channel, that is, synchronous update mode. see table 14 for the ldac register mode of operation. see table 16 for contents of the input shift register during the ldac register setup command. this flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously . table 14. ldac register mode of operation ldac bits (db3 to db0) ldac mode of operation 0 normal operation (default), dac register update is controlled by write command. 1 the dac registers are updated after new data is read in on the falling edge of the 24 th sclk pulse. internal reference s etup the on - chip reference is off at power - up by default. this reference can be turned on or off by setting a software programmable bit, db0 , in the control regist er. table 15 shows how the state of the bit corresponds to the mode of operation. command 111 is reserved for setting up the internal reference (s ee table 8 ). table 16 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. table 15 . reference set up register internal reference setup register (db0) action 0 reference off (default) 1 reference on table 16. 24- bit input shift register contents for ldac setup command for the AD5624R/ad5644r/ad5664r db 23 to db 22 (msb) db21 db20 db19 db18 db17 db16 db15 to db4 db3 db2 db1 db0 (lsb) x 1 1 0 x x x x dac d dac c dac b dac a dont care command bits (c2 to c0) address bits (a2 to a0); dont care dont care set bit to 0 or 1 for required mode of operation on respective channel table 17 . 24- bit input shift register contents for internal reference setup command db 23 to db 22 (msb) db21 db 20 db19 db18 db17 db16 db15 to db1 db0 (lsb) x 1 1 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0) dont care reference setup register
AD5624R/ad5644r/ad5664r data sheet rev. c | page 24 of 28 microprocessor inter facing AD5624R/ad5644r/ad5664r to black fin adsp - bf53x interface figure 58 shows a serial interface between the ad 5624r/ ad5644r/ad5664r and the black fin ? adsp - bf53x micro - processor. the adsp - bf53x processor family incorporates two dual - channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the AD5624R/ad5644r/ad5664r, the setup for the interface is that the dt0pri dri ves t he din pin of the AD5624R/ ad5644r/ad5664r, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. figure 58 . black fin adsp - bf53x interface to AD5624R/ad5644r/ad5664r AD5624R/ad5644r/ad5664r to 6 8hc11/68l11 interface figure 59 shows a serial interface between the AD5624R/ ad5644r/ad5664r and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the AD5624R/ ad5644r/ad5664r, while the mosi output drives the serial data line of the dac. the sy nc signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are that the 68hc11/68l11 is configured with its cpol bit as 0 and its cpha bit as 1. when data is transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as described previously , data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/ 68l11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the AD5624R/ad5644r/ad5664r , pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac; pc7 is taken high at the end of this procedure. figure 59 . 68hc11/68l11 interface to AD5624R/ad5644r/ad5664r AD5624R/ad5644r/ad5664r to 80c51/80l51 interface figure 60 shows a serial interface between the AD5624R/ ad5644r/ad5664r and the 80c51/80l51 microcontroller. the setup for the interface is that the txd of the 80c51/80l51 drives sclk of the AD5624R/ad5644r/ad5664r, while rxd drives the s erial data line of the part. the sync signal is derived from a bit - programmable pin on the port. in this case, port line p3.3 is used. when data is transmitted to the AD5624R/ad5644r/ad5664r, p3.3 is taken low. the 80c51/80l51 transmits d ata in 8 - bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in lsb first format. the AD5624R/ ad5644r/ad5664r must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. figure 60 . 80c51/80l51 interface to AD5624R/ad5644r/ad5664r AD5624R/ad5644r/ad5664r to microwire interface figure 61 shows an interface between the AD5624R/ad5644r/ ad5664r and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5624R/ ad5644r/ad5664r on the rising edge of the sk. figure 61 . microwire interface to AD5624R/ad5644r/ad5664r AD5624R/ ad5644r/ ad5664r 1 adsp-bf53x 1 sync tfs0 din dtopri sclk tsclk0 1 additional pins omitted for clarity. 05856-039 68hc11/68l11 1 sync pc7 sclk sck din mosi 1 additional pins omitted for clarity. AD5624R/ ad5644r/ ad5664r 1 05856-040 80c51/80l51 1 sync p3.3 sclk txd din rxd 1 additional pins omitted for clarity. AD5624R/ ad5644r/ ad5664r 1 05856-041 microwire 1 sync cs sclk sk din so 1 additional pins omitted for clarity. AD5624R/ ad5644r/ ad5664r 1 05856-042
data sheet AD5624R/ad5644r/ad5664r rev. c | page 25 of 2 8 applications information using a reference as a power supply for the AD5624R/ad5644r/ ad5664r because the supply current r equired by the AD5624R/ad5644r/ ad5664r is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 62 ). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage referen ce outputs a steady supply voltage for the AD5624R/ad5644r/ ad5664r (see figure 60 ). if the low dropout re f195 is used, it must supply 450 a of current to the AD5624R/ad5644r/ ad5664r with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k? load on the dac output) is 450 a + (5 v/5 k?) = 1.45 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in a 2.9 ppm (14.5 v) error for the 1.45 ma current drawn from it. this corresponds to a 0.191 lsb error. figure 62 . ref195 as power supply to the AD5624R/ad5644r/ad5664r bipolar operation us ing the AD5624R/ad5644r/ad56 64r the a d5624r/ad5644r/ad5664r have been designed for single - supply operation, but a bipolar output range is also possible using the circuit in figure 63. the circuit gives an output voltage range of 5 v. r a i l - to - rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the out put voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd dd out 536 , 65 where d represents the input code in decimal (0 to 65 , 536). with v dd = 5 v, r1 = r2 = 10 k?, v 5 536 , 65 10 ? ? ? ? ? ? ? = d v out this is an output voltage range of 5 v, with 0x0000 corre - sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. figure 63 . bipolar operation with the AD5624R/ad5644r/ad5664r using AD5624R/ad5644 r/ad5664r with a galvanically isolate d interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common - mode voltages that might occur in the area where the dac i s functioning. isocouplers provide isolation in excess of 3 kv. the AD5624R/ad5644r/ad5664r use a 3 - wire serial logic interface , so the adum130x 3 - channel digital isolator provides the required isolation (see figure 64 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v s upply required for the AD5624R/ ad5644r/ad5664r. figure 64 . AD5624R/ad5644r/ad5664r with a galvanica l ly isolated interface 3-wire serial interface sync sclk din 15v 5v v out = 0v to 5v v dd ref195 AD5624R/ ad5644r/ ad5664r 05856-043 3-wire serial interface 5 n? +5v ?5v ad820/ op295 +5v AD5624R/ ad5644r/ ad5664r v dd v out 5 n? 5v 0.1f 10f 05856-044 0.1f 5v regulator gnd din sync sclk power 10f sdi sclk data AD5624R/ ad5644r/ ad5664r v out v ob v oa v oc v dd v ic v ib v ia adum1300 05856-045
AD5624R/ad5644r/ad5664r data sheet rev. c | page 26 of 28 power supply bypassi ng and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the AD5624R/ ad5644r/ad5664r should have separate analog and digital sections, each having its own area of the board. if the ad 5624r/ ad5644r/ad5664r are in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the AD5624R/ad5644r/ad5664r. the power supply to the AD5624R /ad5644r/ad5664r should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitor is the tantalum bead type. it is i mportant that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low imped - ance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals s hould be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2 - l ayer board.
data sheet AD5624R/ad5644r/ad5664r rev. c | page 27 of 28 outline dimensions figure 65 . 10 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters figure 66 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifie r 15 max 0.95 0.85 0.75 0.15 0.05
AD5624R/ad5644r/ad5664r data sheet rev. c | page 28 of 28 figure 67 . 12 - ball wafer level chip scale package [wlcsp] (cb - 12 - 9) dimensions shown in millimeters ordering guide model 1 temperature range accuracy internal reference package description package option branding AD5624Rbcpz - 3r2 ?40c to +105c 1 lsb inl 1.25 v 10 - lead lfcsp_wd cp -10 -9 d7l AD5624Rbcpz - 3reel7 ?40c to +105c 1 lsb inl 1.25 v 10 - lead lfcsp_wd cp -10 -9 d7l AD5624Rbcpz - 5r2 ?40c to +105c 1 lsb inl 2.5 v 10 - lead lfcsp_wd cp -10 -9 dbz AD5624Rbcpz - 5reel7 ?40c to +105c 1 lsb inl 2.5 v 10 - lead lfcsp_wd cp -10 -9 dbz AD5624Rbrmz - 3 ? 40c to +105c 1 lsb inl 1.25 v 10 - lead msop rm - 10 d7l AD5624Rbrmz - 3reel7 ? 40c to +105c 1 lsb inl 1.25 v 10 - lead msop rm -10 d7l AD5624Rbrmz -5 ? 40c to +105c 1 lsb inl 2.5 v 10 - lead msop rm -10 d7v AD5624Rbrmz - 5reel7 ? 40c to +105c 1 lsb inl 2.5 v 10 - lead msop rm -10 d7v ad5644rbrmz -3 ? 40c to +105c 4 lsb inl 1.25 v 10 - lead msop rm -10 d7e ad5644rbrmz - 3reel7 ? 40c to +105c 4 lsb inl 1.25 v 10 - lead msop rm -10 d7e ad5644rbrmz -5 ? 40c to +105c 4 lsb inl 2.5 v 10 - lead msop rm -10 d7d ad5644rbrmz - 5reel7 ? 40c to +105c 4 lsb inl 2.5 v 10 - lead msop rm -10 d7d ad5664rbcbz - 3rl7 ? 40c to +105c 16 lsb inl 1.25 v 12 ball wlcsp cb -12 -9 ad5664rbcpz - 3r2 ? 40c to +105c 16 lsb inl 1.25 v 10 - lead lfcsp_wd cp -10 -9 d73 ad5664rbcpz - 3reel7 ? 40c to +105c 16 lsb inl 1.25 v 10 - lead lfcsp_wd cp -10 -9 d73 ad5664rbrmz - 3 ? 40c to +105c 16 lsb inl 1.25 v 10 - lead msop rm - 10 d73 ad5664rbrmz - 3reel7 ? 40c to +105c 16 lsb inl 1.25 v 10 - lead msop rm -10 d73 ad5664rbrmz -5 ? 40c to +105c 16 lsb inl 2.5 v 10 - lead msop rm -10 d75 ad5664rbrmz - 5reel7 ? 40c to +105c 16 lsb inl 2.5 v 10 - lead msop rm -10 d75 eval - ad5664rebz evaluation board 1 z = rohs compliant part. a b c d 0.650 0.595 0.540 1.705 1.665 1.625 2.285 2.245 2.205 1 2 3 bot t om view (bal l side up) t op view (bal l side down) end view 0.340 0.320 0.300 1.50 ref 1.00 ref 0.50 bsc bal l a1 identifier 08-31-2012- a sea ting plane 0.270 0.240 0.210 0.380 0.355 0.330 coplanarity 0.05 ? 2006 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05856 - 0 - 4/13(c)

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